The present invention concerns transfer of data over a microprocessor bus and pertains particularly to a microprocessor which is able to use both multiplexed addressing and non-multiplexed addressing.
Central processing units (CPUs) and microprocessor generally have four types of input and output signals: address signals, data signals, control and status signals and power signals. The address signals are generally placed on an address bus. The address signals are output signals used to indicate the target of a data access. The access is generally a read of data from a data storage device or a write of data to a data storage device.
The data signals are generally transferred over a data bus. Data signals are bidirectional signals used to transfer instruction and data to and from the CPU or microprocessor.
The control and status signals include, for example, bus transfer control signals, interrupt signals, control signals, test signals, emulation control signals, status signals, clocking signals, and so on. The particular combination of control and status signals used by a CPU or microprocessor is specific to the individual CPU or microprocessor.
The power signals generally include one or more power signals and a reference (or return) signal.
For example, the 680xx family of microprocessor, available from Motorola Communications and Electronics Inc., having a business address at 801 Ames Avenue, Milpitas, Calif., uses separate address and data buses (Non-multiplexed) on its 680xx processors and "Coldfire" processors. Motorola's 680xx family of processors allows the data bus width to dynamically change on a transfer by transfer basis based on control signals exchanged during the transfer.
In order to reduce complexity and manufacturing cost of integrated circuits and the packaging of integrated circuits, as well as to reduce the complexity of board level trace routing, it is desirable to reduce the number of pins used by a packaged microprocessor. For this reason it is common to find microprocessors which provide multiplexed address and data bus signals.
Multiplexing address signals and data bus signals is accomplished by utilizing a single set of input/output (I/O) pins for the microprocessor and by time multiplexing the address and data on this single set of I/O pins. These I/O pins together may be referred to as a multiplexed address and data bus. Using such a multiplexed address and data bus, the address is generally transferred over the multiplexed address and data bus during the first phase of an access cycle and then the data is transferred over the multiplexed address and data bus during the remaining phases of the transfer.
While this approach can reduce the CPU cost, it can increase the system cost when the CPU is interfaced with devices which do not support multiplexed address and data buses. In such cases, additional circuitry is required to extract the address during the address phase of the transfer. Likewise, when a system employs a CPU with non-multiplexed address and data buses, system cost may increase when the CPU is interfaced with devices with multiplexed buses.
For example, Intel i960 central processing units available from Intel Corporation, having a business address of 2200 Mission College Boulevard, Santa Clara, Calif. 95050, use multiplexed address and data. Intel i960 processors divide the addressable memory space into fixed sized regions. Each region has a corresponding dedicated configuration register which contains region specific information as to the bus width of target devices and the number of cycles required to complete a transfer. This information is used dynamically for each transfer throughout the addressable memory and I/O space. The configuration information is initially programmed when the device is powered by reading from a specific memory region in a required memory device.